The November 2025 edition of DesignFutures delivered a concentrated and highly technical overview of the changes shaping modern system and semiconductor design. This online event brought together experts from YorChip, Axelera AI, PrimeSoc Technologies, DiffLogic, and Siemens EDA to discuss advances in chiplet architectures, verification scalability, interface IP complexity, and new logic models for AI inference.
The programme aligned with three themes: chiplet-based system design, AI-supported workflows, and new markets and technologies that are beginning to influence design decisions across the industry.
Chiplets for Everyone
Kash Johal from YorChip opened with a comprehensive market and technology overview. Chiplets are most commonly deployed in high-value devices, ranging from around $30 to the thousands, driven by the yield benefits of splitting large monolithic dies. As shown in Figure 1, these devices dominate high-performance computing and data centre applications where bandwidth and performance requirements justify the higher cost. The same market view also highlights the emerging edge AI segment in the $2–$20 range, which YorChip identifies as the next significant growth opportunity for physical AI applications such as robots, autonomous systems, wearables, and embedded perception engines.
Figure 1: Chiplet Market Segments – HPC/Data Centre vs Edge AI (YorChip, Nov 2025).
This figure illustrates the contrast between high-value data centre chiplets priced above $30 and the lower-cost edge AI segment, priced between $2 and $20. It shows that current adoption is concentrated in expensive devices, while the most significant projected growth comes from low-power, low-cost edge systems that require frequent algorithm updates.
Despite this opportunity, several barriers limit broader chiplet adoption. Interoperability remains constrained, and total cost is difficult to model due to differences in packaging. UCIE variants rely heavily on analogue PHY behaviour, which is challenging to port and verify in low-cost or field-deployed devices. High-speed serialisation introduces skew and deskew issues. YorChip presented UCI3D as a more practical alternative, offering a fully digital PHY suitable for devices costing under $10 with easier portability across technology nodes. Chiplet management also remains unresolved, with boot sequencing, ID assignment, test, and security still handled outside the chiplet. Achieving wider adoption will require simpler PHYs, better interoperability frameworks, and clearer management standards.
Multisim for Scalable Chiplet and SoC Verification
Antoine Madec of Axelera AI presented Multisim, an open-source SystemVerilog and DPI-based platform created to overcome the performance limitations of large-scale simulation. Classical simulation offers high realism but can fall below one kilohertz on complex SoC designs, while emulation improves speed but is costly and reduces visibility. As shown in Figure 2, Multisim restructures a monolithic DUT into a distributed model in which a central server simulation hosts the NoC, memory subsystem, and global environment, and multiple CPU instances run as independent client simulations connected via DPI sockets. This architecture enables accurate multi-process scaling and avoids the bottlenecks associated with cycle-accurate synchronisation.
Figure 2: Multisim server–client architecture showing how a monolithic DUT is partitioned into a single server simulation and multiple client simulations connected via SystemVerilog DPI (Axelera AI, Nov 2025).
This figure illustrates how Multisim achieves scalable performance by mapping each CPU instance to a free-running client simulation. In contrast, the server simulation coordinates global traffic through the NoC and the memory controller.
The platform supports AXI, APB, and quasi-static wrappers, and the slides demonstrated 64 CPU clients connected via 128 circuits, with simulation time remaining stable as more clients were added. In an AXI-based example, sixty-four CPUs produced three hundred and twenty circuits with only a marginal increase in runtime. Multisim is well-suited for multi-company and multi-tool collaboration because the DPI interface works with Questa, VCS, Xcelium, Verilator, and Python-based models. Two usage modes were highlighted: early functional verification can remove the UCIE subsystem entirely for maximum performance, while cycle-sensitive testing retains UCIE within the server simulation. Future improvements include support for 4-state logic and transaction logging to simplify debugging.
High Speed Interface IP Challenges
PrimeSoc Technologies highlighted the increasing complexity of next-generation interface IP such as PCIe Gen 7, CXL 3, and UCE 2.x. These controllers operate at frequencies above 2 GHz and can contain multi-million-gate designs with extensive internal data paths. As shown in Figure 3, modern protocols require multi-TLP handling, tightly packed transmit and receive logic, and multiple interface widths across both the application and PHY sides. PCIe Gen 7 x16 paths can exceed two thousand bits, and additional constraints come from complex specification requirements such as flit alignment, flit and non-flit conversions, low power domain transitions, and IDE protection modes.
Figure 3: Summary of design and verification challenges for high-speed interfaces, including PCIe, UCIe, and CXL, covering multi-TLP logic, wide data paths, flit alignment, IDE handling, and dynamic lane resizing (PrimeSoc Technologies, Nov 2025).
This figure captures the breadth of challenges encountered when implementing next-generation interface IP, including timing closure at very high frequencies and the protocol-level behaviours that significantly increase design and verification effort.
Verification becomes even more demanding under these constraints. More than forty configuration variables can produce over ten thousand possible test cases for a single IP or subsystem, and examples shown in the slides included dynamic lane resizing in the L0P state, strict CXL flit alignment, and enumeration scenarios in which a Gen 6 controller enumerates as Gen 4 on the FPGA due to clock limitations. Interoperability improves when standard interfaces such as AXI or PIPE are used, whereas proprietary behaviours require case-by-case integration and additional debug effort.
Differentiable Logic Gate Networks
DiffLogic presented an approach in which machine learning models are trained directly as logic circuits rather than as numerical networks. During optimisation, each node is treated as a smooth relaxation over the space of sixteen Boolean functions, allowing gradient-based training to identify the most suitable operation. Once training completes, the network collapses into a fixed Boolean circuit that evaluates in nanoseconds and maps efficiently to FPGA and ASIC targets. As shown in Figure 4, the method produces continuous intermediate values during training before settling into a deterministic inference path. This deterministic inference path avoids floating-point computation and enables very low-latency, hardware-friendly execution.
Figure 4: Illustration of a differentiable logic gate network where continuous outputs during training converge to a fixed Boolean circuit that separates two image classes (DiffLogic, Nov 2025).
The examples demonstrated included a CERN classification model implemented with fewer than 100 LUTs and image recognition tasks that achieved significant speed improvements and reduced gate counts compared with alternative hardware ML flows. Additional applications covered logic synthesis, high-throughput intrusion detection, and real-time image enhancement on constrained devices. Training stability for deeper networks is achieved through residual initialisation, logic kernels, and pooling operations that prevent gradients from collapsing.
Questa Developer: Integrated Verification Environment
Siemens EDA presented Questa Developer as a unified verification environment designed to remove the fragmentation that often arises when engineers switch between simulation, static analysis, and formal tools. The environment packages all design information, library mappings, and analysis settings into a single project, allowing teams to move between tasks without rebuilding context. It provides a browser for design exploration, a smart editor with on-the-fly checks, and direct access to schematic and hierarchy views. As shown in Figure 5, the environment provides a single entry point to manage design sources, navigate RTL, trigger static and formal checks, and review results through a single interface. Questa Developer is available as a standalone desktop application or as a VS Code extension, giving users flexibility in integrating the workflow into their existing setups.
Figure 5: The integrated verification environment in Questa Developer, showing design entry, smart editing, source navigation, and static and formal analysis from a single workspace (Siemens EDA, Nov 2025).
The session also introduced agentic capabilities that allow large language models to operate within the environment through a controlled API. These assistants can generate RTL, refine code, create or configure testbenches, and guide tool flows, reducing manual setup effort. The IDE supports automatic FPGA project import, team-friendly project portability, and a plugin system that enables third-party tool integration via scripted extensions. The demonstration highlighted dynamic hierarchy updates, active linting, task management for verification steps, and an agent window for AI-assisted actions, illustrating how the environment brings together design creation, analysis, and debugging within a single, coherent flow.
Explore More Technical Insights
DesignFutures will continue to support engineers as they navigate evolving chip architectures, verification challenges, and new AI-driven methodologies. Explore more technical insights at: https://alpinumconsulting.com/resources/blogs/events
Top comments (0)