The semiconductor industry is under growing pressure to deliver higher performance, lower power consumption, and reduced cost per transistor. However, as process technologies continue to shrink, the traditional monolithic SoC model is reaching both physical and economic limits. Larger dies are more expensive to produce and have lower yield, while not all functions scale efficiently at smaller geometries.
The industry’s answer is chiplet-based design. Chiplets enable splitting complex systems into smaller, specialized dies that are easier to manufacture, optimize, and verify. They offer a practical path forward for innovation, cost control, and sustainable scaling.
1. Chiplets and the Semiconductor Industry Problems They Solve
As semiconductor nodes shrink, the cost per square millimeter of silicon rises significantly. Larger monolithic chips suffer from lower yield because a single defect can make an entire die unusable. Such yield losses make traditional SoCs increasingly expensive to design and fabricate. The figure below illustrates how chiplet-based architectures overcome these constraints through flexible, multi-die partitioning.
Figure 1: Comparison of monolithic SoC and chiplet-based architectures, illustrating yield and modular integration advantages. Source: imec (via Milos Mirosavljevic, Infineon Technologies)
Chiplets address this by dividing a design into smaller, reusable dies, each optimized for a specific function. Smaller dies improve yield and reduce production cost. Instead of manufacturing a single large chip using an advanced process, designers can mix technologies to achieve the best price–performance balance.
For example, a 22 nm analogue chiplet can be integrated with a 1 nm high-performance graphics processor. This approach allows each function to be implemented on the most appropriate process node, improving efficiency and reducing cost. It also supports faster design cycles by reusing proven components across product generations.
2. The Vision for Chiplets
Chiplets represent the next stage in multi-silicon integration, in which multiple dies operate as a single system. Today, most chiplet-based designs are proprietary. Companies such as AMD, Intel, and Apple typically integrate two or three chiplets per package, built and verified in-house. These systems deliver impressive results but remain closed ecosystems. The long-term vision is more ambitious. In the future, designers will be able to purchase chiplets from different vendors and combine them off the shelf to create new systems. This mix-and-match model could enhance design flexibility, reduce time-to-market, and enable true reusability of verified components.
Achieving this vision depends on interoperability and standardisation. The UCIe (Universal Chiplet Interconnect Express) standard is a significant step in this direction, providing a universal die-to-die interconnect. However, practical challenges remain. The UCIe PHY layer introduces analogue complexity, alignment and skew issues, and high packaging cost. These factors limit adoption outside of high-end applications such as data centres. For broader use, especially in edge and consumer devices, a more straightforward, more robust approach is needed. Emerging digital PHYs such as UCI3D offer promising solutions. They reduce power and cost, simplify porting across nodes such as 28 nm and 40 nm, and support new technologies, including optical interconnects. These digital PHYs enable chiplets to be deployed in low-cost, low-power markets such as wearables, robotics, and edge AI.
However, chiplet interfaces are still largely static. Once defined, they cannot easily be upgraded, which makes backward compatibility and future-proofing key considerations in system planning.
3. Problems Solved: Economic and Design Impact
Chiplets are helping to solve several of the semiconductor industry’s key challenges:
- Yield improvement: Smaller dies increase usable output per wafer and reduce defect-related losses.
- Cost optimisation: *Each chiplet is fabricated on the most appropriate node, lowering total system cost.
*- Heterogeneous integration: Designers can efficiently combine analogue, digital, memory, and AI functions.
- Scalability and flexibility: *Only selected chiplets need redesign for product upgrades, thereby reducing time-to-market.
*- Supply chain resilience: Modular sourcing from multiple vendors reduces dependency on any single supplier.
- Sustainability: Reusing validated chiplets and packaging reduces development overheads and waste.
Chiplets enable continued performance and functionality gains while maintaining economic viability at advanced nodes. They extend Moore’s Law through architectural innovation, rather than pure transistor scaling.
4. The Test Impact
Building on these design and cost advantages, testing now plays a crucial role in ensuring chiplet-based systems deliver consistent quality, cost efficiency, and interoperability. The OCP Chiplet Test Workstream White Paper highlights the need for unified Design-for-Test (DFT) strategies, hierarchical test architectures, and reuse of chiplet-level test data at the system level. Concepts such as Known Good Die (KGD) testing, assembly yield recovery, and standardised interfaces (IEEE 1149.1, 1687, 1838, and 3405) are central to ensuring reliability across multi-die assemblies. The paper further emphasises that structural, functional, and system-level testing must evolve together to enable an open and cost-effective chiplet marketplace.
For more details, see the official OCP D2D Interface Test Paper (2025)
5. The Verification Impact
While chiplets address the physical and economic limits of semiconductor design, they create new verification challenges. Each chiplet may come from a different team, vendor, or process technology, making system-level validation far more complex.
Verification must now include:
- Interface compliance across standards such as UCIe and AXI.
- Power and thermal interaction between dies.
- Timing and synchronization across die-to-die links.
- Security aspects such as chiplet identification, boot integrity, and root-of-trust management.
Traditional SoC verification environments are not well-suited to this distributed architecture. Multisim, presented by Antoine Madec of Axelera AI, provides one solution. It uses SystemVerilog/DPI and TCP/IP to connect multiple simulators, allowing distributed simulation across different vendors’ tools. This methodology improves scalability and enables system-level testing without sacrificing functional accuracy.
New integrated verification environments also bring formal, static, and simulation-based analysis together in a single project framework. These platforms reduce context switching, promote reuse of assertions, and automate debugging across complex, multi-die systems.
Together, such advances demonstrate how verification must evolve to support the multi-silicon era. The next step for the industry is to create scalable and collaborative verification flows that ensure trust, reliability, and performance across multi-die systems.
6. The Path Forward
Chiplets are redefining semiconductor design by offering a sustainable approach to scaling performance, reducing costs, and enabling heterogeneous integration. Their success now depends on three critical factors: interoperability, affordable packaging, and scalable verification.
As the ecosystem matures, design and verification methodologies must evolve together. Standards such as UCIe and new developments in digital PHYs will enable broader adoption, while collaborative verification platforms will ensure reliability across diverse dies and vendors.
The semiconductor industry is moving from transistor scaling towards architectural scaling. Chiplets will play a central role in this transformation by enabling modular, efficient, and accessible innovation. Although chiplets will not simplify design, they have the potential to make innovation more widely attainable.
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